1. Field of the Invention
The present invention relates to network interface devices for interconnecting host processors with a communication network, and more particularly to the processing of specific types of packets at the network interface.
2. Description of Related Art
Management of computer networks is accomplished in many systems by a central network management station which has access to end stations in the network for management functions. Several specialized control packets have been developed, which are transmitted to the end stations in support of these management functions. Some of these control packets are suitable for processing at the network interface, rather than after delivery to the host system on which the network interface is attached.
In one prior art system, network interface devices are configured to capture packets while the host system is not active, including xe2x80x9cwake upxe2x80x9d packets using resources on the interface card. See, NIC Device-Class Power Management Specification, Version 1.0a, Nov. 21, 1997; Microsoft Corporation. (See, http://www.microsoft.com/hwdev/specs/PMref/PMnetwork.htm). The NIC Device-Class Power Management Specification handles the situation in which a host processor running Windows or another operating system OS wants to go to sleep, yet allow others to access any shared directories or devices it might have offered to the network. So the host OS passes the adapter a set of filters (filter=bit mask to specify which bytes are interesting and a byte string for comparing the interesting bytes) which the adapter should use. If a packet comes in matches the filters, then the adapter wakes up, and signals power management resources in the host system.
As the speed and complexity of networks increase, more types of packets are suitable for being handled by processors in the smart interface cards. In order for a processor to react to the contents of packets, it must have resources to read the relevant part of the packet, and execute the appropriate instructions, as data is passing through the network interface card. If the processor cannot keep up with the network, then packets will be dropped and network throughput will suffer. Relatively powerful processors by today""s standards are required to keep up with fast networks, such as 100 Megabit per second or Gigabit per second Ethernet. However, such powerful processors add significant cost to the network interface cards. This imbalance in the cost of processing power and network speed is likely to continue to arise in a variety of settings as technology advances on both fronts.
Accordingly, it is desirable to provide a network interface capable of handling certain specialized packets, without incurring the increased costs associated with powerful on chip, or on-board, processors.
The present invention provides a network interface card, or an interface to other types of communication channels, with limited intelligence, implemented using a relatively slower, and lower cost embedded processor, supported by dedicated hardware logic for the purposes of intercepting certain packets being received via the network. In particular, the present invention provides an interface that comprises the first port on which incoming data is received at the data transfer rate of the network, a buffer coupled to the port that stores received packets, and a second port coupled with the buffer through which transfer of packets to the host is executed. Packet filters are coupled to the first port which identifies packets being stored in the buffer that have one of the plurality of variant formats. A processor is coupled with the buffer as well, and is responsive to the packet filter to process identified packets in the buffer. In this manner, the processor is able to operate at a slower speed, such that the processing time for a typical packet is greater than the amount of time that is consumed by storing a typical packet in the buffer. Because the processor is only required to handle packets identified by the dedicated packet filter logic, it need not have the capability to keep up with the entire data stream.
In various embodiments, the packets intercepted according to the present invention include a remote control packet allowing a management console to remotely reboot the targetted computer. Such a packet would simply be discarded by the interface processor and an action performed to reboot the computer, such as by sending a command to the host using a management interface like the SMBus (See, Smart Battery System Specificationsxe2x80x94System Management Bus Specification, Rev. 1.0, (1995) Benchmarq Microelectronics, Inc., et al.).
In another embodiment the intercept technique of the present invention is used for tracking the host computer""s IP address. The processor on the interface card might need to know the local internet protocol IP address of its host This can be complicated if Dynlamnic Host Configuration Protocol DHCP, or another protocol for assigning dynamic IP addresses to devices on a network, is in use by which the IP address might change over time. By trapping the DHCP packets and examining them before passing them to the host, the interface card can track the changes in the IP address as they happen, and do it without adding any extra instructions to the critical code paths on the host which might increase CPU utilization or reduce performance. The invention is particularly suited to environments in which the host system is actively handling communications and other processing tasks, and in which the adapter is able to take over some specialized tasks without interfering with the active processing in the host system.
For example, in one embodiment the first port comprises a medium access control unit configured for network having a data rate of 100 Mbps or higher. In this example, a simple RISC processor operating with a processor clock of 25 MHz, and an effective rate of executing instructions of less than 25 MHz, is provided on the network interface card.
According to various aspects of the invention, the packet filter comprises one or more match logic circuits. The match logic circuits comprise mask logic circuits that store a mask identifying selected bytes within a packet of a particular format in the plurality of variant formats. Logic circuits to generate a hash in response to the selected bytes, such as cyclical redundancy code CRC hash logic, are coupled to the incoming port on the device. A comparator compares the output of the hash logic with an expected hash. If a match is detected, then the processor is signaled that the packet being received is, or may be, suitable for processing on the network interface card. The hash used by be imperfect, so that occasional packets that need not be processed by the local processor are trapped.
According to another aspect of the invention, the mask logic within the pattern match logic includes a mask and a mask modifier. The mask logic uses the mask modifier in response to the packet format, so that variations of a particular format can be handled with a single set of pattern match logic circuits. For example, certain packets may have a format accommodating optional fields. The mask modifier is applied to account for the presence or absence of data in the optional fields, while selecting the bytes for input to the hash logic. For example the mask is modified by logic which causes certain bytes to be skipped by the mask and hash generator.
According to various embodiments of the invention, the buffer comprises a First-In-First-Out (FIFO) buffer, a page mode RAM buffer, or other memory on or off the chip. As packets are supplied to the buffer, logic on the network interface card inserts a control field, such as a header, in the buffer. The results of the pattern match logic are written as a flag, or flags, in the control field to indicate whether the packet has a particular one of the plurality of variant formats. When a particular packet in the FIFO buffer reaches a stage for upload to the host computer, the logic on the network interface card issues an interrupt to the processor on the network interface card if a flag is set. In response to the interrupt, the packet in the FIFO buffer is processed locally on the network interface card. If the FIFO buffer overflows during the processing of the packet, then packets may be lost. However, because of the relatively small number of packets to be processed by the local processor, very few packets will be lost in the typical network.
According to yet another aspect of the invention, a single integrated circuit for an Ethernet network interface card comprises an Ethernet medium access control (MAC) unit on which incoming data is received at a data transfer rate of 100 Mbps or higher. A FIFO buffer is coupled to the MAC unit. A host port is coupled with the FIFO buffer through which transfer of packets to the host is executed. Packet filters are included on the chip as discussed above with mask logic, hash logic and a comparator used for signaling an on chip processor that a packet having a particular format is being stored in the FIFO buffer. At least a particular format in the plurality of variant formats supports packets having an optional field as mentioned before. Mask modifier logic is included to modify the mask to account for the optional field. The optional field comprises in various embodiments a virtual local area network (VLAN) tag or a subnetwork attachment point (SNAP) header.
Accordingly, an integrated circuit network interface device for a high speed network medium is provided with the relatively slow, low-cost embedded processor. Hardware pattern matching logic supports pattern matching at the speed of the incoming packet stream, and signals the embedded processor when a packet having one of the plurality of variant formats is detected. Further, the embedded pattern matching logic uses minimum space on the chip, by for example, including logic to handle optional fields in particular packet formats in a single pattern matching engine.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description and the claims which follow.